The present invention relates to a data transfer apparatus for a data processing system.
A conventional data transfer apparatus of this type includes a plurality of memory access flags to perform memory access. Each memory access is assigned to the corresponding channel. As shown in FIG. 2, a memory access time slot of one channel is assigned to a specific machine cycle of one period at the time of memory access. For example, in the memory access, data having a specific data length, e.g., 8-byte data, is exchanged between a memory and an input/output device within a predetermined period, e.g., four machine cycles each assigned to four channels. A memory access buffer is arranged for only one memory access cycle corresponding to, e.g., 8-byte data.
In such a data transfer apparatus, an upper limit of memory access performance of one channel is determined. It is generally considered that the memory access speed is high, and is not lower than a transfer speed of an input/output device.
However, an input/output device such as a semiconductor disk, has been developed, and generations of main frame and peripheral system apparatus do not coincide with each other. Therefore, an input/output device having a transfer speed higher than the memory access speed has been required.
In such a case, speed matching is performed between the input/output device and the data transfer apparatus through an adapter such as a local memory for buffering one block of a data record of the input/output device. However, this speed matching causes an increase in hardware, and a delay of an I/O time period occurs by an access time of the local memory. Therefore, such high-performance input/output device cannot be efficiently used.